1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a fin transistor, which is constructed to improve performance and yield in a semiconductor device.
2. Description of the Related Art
The design rule calling for increasingly shrinking semiconductor memory device in terms of size means that the channel length and the channel width of a transistor formed therein must decrease while both the doping concentration of the junction regions and the junction leakage current increase due to formation of high electric field. This causes difficulty in obtaining a required threshold voltage when a conventional transistor, which has a two-dimensional planar channel structure, is used in a highly integrated semiconductor device. This also causes limitations in improving the refresh characteristics.
In response to these problems, some known researches produced a transistor, which has a three-dimensional channel structure capable of increasing a channel length, known as the “fin transistor” having a three-dimensional channel structure.
In forming a fin transistor, a field oxide layer (which exists in a field region) is entirely or partially etched to expose an active region. Hence, as the active region projects, the fin transistor has a three-dimensional channel structure, whereby it is possible to improve current drive characteristic. As a consequence, the fin transistor has drawn attention as it may be an ideal structure for realizing a next generation ultra high integration device. In particular, the fin transistor is considered to have an advantage in increasing a refresh time interval in a memory device.
Meanwhile, as the degree of integration of a device increases, it has been difficult to form a field oxide layer for isolating active regions from one another. Specifically, as the gap between field regions is narrowed, it has been difficult to fill a trench with an insulation layer. Therefore, instead of solely using a high density plasma (HDP) oxide layer as an insulation layer for filling a trench, a laminate of a spin on glass (SOG) layer and an HDP oxide layer is advantageously used for filling a trench. That is to say, when filling a trench, the lower portion of the trench is filled by the SOG layer, and the upper portion of the trench is filled by the HDP oxide layer. In this method, the trench can be easily filled irrespective of the depth of the trench.
However, when etching the field oxide layer to project the active region, a problem is caused in that, since the SOG layer having a high etch rate with respect to an etching solution is exposed, the side surfaces of the exposed SOG layer are etched in a subsequent washing process. If the side surfaces of the SOG layer are etched, because a polysilicon layer serving as a gate wiring material is not removed from but remains on the side walls of the etched SOG layer, shorts can be caused between gates and between gate lines and bit lines, whereby yield is decreased in the manufacture of a semiconductor device. Also, due to the presence of a parasitic capacitance, device characteristic can be deteriorated such as the reduction of the driving speed of the device.